FIG. 1 is a block diagram showing the construction of a DLL circuit disclosed in Japanese Patent Laid-Open No. 17179/1997 (hereinafter referred to as “first conventional technique”).
The DLL circuit according to the first conventional technique comprises; a four-phase basic clock generation circuit 541 which generates four phase clocks different from one another in phase by 90 degrees relative to an input clock 601 having a frequency f; a phase detection circuit 542 for detecting a phase relationship between the input clock 601 and an output clock 603; a phase regulation decision circuit 544 which, upon the input of control signals 608 and 609 output from the phase detection circuit 542, outputs signals 614 and 615 with phase regulation level reduced or increased by given level according to the input levels of the control signals; a phase shifting circuit 543 which, upon the input of signals 610 to 613 output from the four-phase basic clock generation circuit 541, mixes these signals together and executes phase shifting according to the signals 614 and 615 output from the phase regulation decision circuit 544; and an output circuit 545 which permits the input of signals 616 and 617 output from the phase shifting circuit 543 and outputs them as an output clock 603 having a frequency f. The phase detection circuit 542 comprises a phase decision circuit 511 and a level shifting circuit 513 for regulating the level of the signal output from the phase decision circuit 511.
FIG. 2 is a block diagram showing the construction of a DLL circuit disclosed in Publication No. 512966/1997 of the Translation of International Patent Application (hereinafter referred to as “second conventional technique”).
The DLL circuit according to the second conventional technique comprises: a duty cycle correction amplifier 700 which corrects the duty cycle of an input reference clock signal and outputs a duty cycle corrected signal; a phase detector 710 which compares the phase of a clock signal output from the DLL circuit with the phase of a reference clock signal and generates and outputs a signal which indicates whether the phase of the output clock signal is in advance of or delays from the phase of the reference clock signal; a charge pump 720 (preferably a differential charge pump) which is driven by a signal output from the phase detector 710 and generates an output current according to the output signal: a phase shifter 730 into which the duty cycle corrected signal, a signal output from the phase detector 710, and a current output from the charge pump 720 are input and which performs phase shifting of the duty cycle corrected signal to a direction indicated by the signal output from the phase detector 710 and outputs a phase s corrected signal; a second duty, cycle corrector 740 into which the phase corrected signal output from the phase shifter 730 and an output clock signal are input to correct the duty cycle of the output clock signal to a desired value; and a buffer amplifier 750 for amplifying the output clock signal to a predetermined amplitude.
DLL circuits are divided into two types, that is, a type wherein the delay of an input signal is regulated to digitally control the phase, and a type wherein m signals, wherein m is an integer of two or more, different from each other in phase are generated from an input signal and are then combined to control the phase in an analog manner.
A typical example of devices, in which DLL circuits are used, is synchronous DRAM (dynamic random-access memory). The control of the operation of double data rate-type (DDR-type) devices, which are operated in synchronization with a complementary clock signal, in particular, among the synchronous DRAMS is carried out using a signal having a duty falling within a given range and further requires a timing signal other than one cycle or half cycle unit of a reference clock signal.
In DLL circuits wherein the phase is digitally controlled, a reference clock signal is delayed to generate desired timing. This makes it difficult to generate timing other than one cycle or half cycle unit of the reference clock signal.
For this reason, in devices which additionally require a timing signal other than one cycle or half cycle unit of the reference clock signal, such as DDR-type synchronous DRAMs, it is a common practice to use DLL circuits, which control the phase in an analog manner, as shown in the above-described first and second conventional techniques.
The DLL circuits, which control the phase in an analog manner, however, involve a problem that lowering the operating frequency does not reduce current consumption.
Specifically, in DLL circuits which digitally control the phase, CMOS transistors are used to constitute the circuits. Therefore, lowering the operating frequency results in lowered current consumption.
On the other hand, in DLL circuits which control the phase in an analog manner, as can be seen from the second conventional technique, a differential amplifier circuit provided with a constant-current source is used to generate a desired timing signal. For example, a more specific circuit diagram of a phase detector as a major element in the DLL circuit according to the second conventional technique is shown in FIG. 3, and a more specific circuit diagram of a duty cycle correction amplifier as a major element in the DLL circuit according to the second conventional technique is shown in FIG. 4. Further, a block diagram of a phase shifter as other element in the DLL circuit according to the second conventional technique is shown in FIG. 5, and a block diagram of a phase corrector contained in the phase shifter shown in FIG. 5 is shown in FIG. 6. As can be seen from FIGS. 3 to 6, in all the cases, a differential amplifier circuit provided with a constant-current source is used.
In general, the current value of the constant-current source in the differential amplifier circuit is fixed to a value large enough to correspond to the highest operating speed from the viewpoint of realizing high-speed operation. Therefore, lowering the operating frequency does not contribute to a reduction in current consumption.
When DLL circuits, in which the above differential amplifier circuit has been extensively used, are used at a significantly lower speed than the highest operating speed, they can be operated even when the current value of the constant-current source in each differential amplifier circuit is considerably low. The conventional DLL circuits, however, do not have any means which can automatically vary the current value of the constant-current source in each incorporated differential amplifier circuit according to the operating speed (frequency of signal input into DLL circuit). Therefore, an attempt to use the conventional DLL circuit, which can cope with a high input signal frequency, also in the case of a low input signal frequency poses a problem or wasteful power consumption.